The present invention relates to a buffer circuit, and more particularly to a fast output buffer circuit giving a full range of output volts.
Such a buffer circuit may comprise a bootstrap circuit of the type used in an integrated circuit known as Intel. 2401 (2K n-channel shift register). This circuit includes an input terminal connected to the gates of first and second field effect transistors. The first transistor constitutes an input transistor and its drain is connected to one side of a bootstrapping capacitor and to a load resistance. The source-drain path of the second transistor is connected in series with the source-drain path of a third field effect transistor and the series combination is connected between a pair of power supply rails. An output terminal is connected to the common connection between the second and third transistors. The gate of the third transistor is connected to the other side of the bootstrapping capacitor and a fourth field effect transistor having its gate-drain shorted together forms a clamp connected between the junction of the other side of the capacitance and the gate of the third transistor and one of the supply rails. One of the disadvantages of this known circuit is that when the input goes from low to high, the gates of the first and second transistors go high and their drains go low, the gate of the third transistor goes low but as the capacitor becomes charged, the gate of the third transistor goes high and in this situation the series connected second and third transistors are both conductive causing an excessive current drain from the supply.
Further in this known circuit it is not possible to predetermine how quickly the circuit will reach full output voltage.
Accordingly, it is desired to provide a buffer circuit which is able to produce a high output quickly, that is to say 18 nS (nanoseconds), while at the same time does not consume too much power.
According to the present invention there is provided a buffer circuit comprising an input, an output, first and second field effect transistors (FETs) having their source-drain paths connected in series between a pair of power supply rails, the junction of said source-drain paths being connected to the output, first and second circuits connected between the input and the gates of the first and second FETs, respectively, said first and second circuits being operative in response to changes in a signal applied to the input to render one of the first and second FETs conductive at any one time, said first circuit including a bootstrapping capacitance having one side connected to the gate of the first FET and another side coupled to an output of a delay circuit, the delay period of which circuit determines the charging time of the capacitance, an input of the delay circuit being coupled to the first-mentioned input, switching means for connecting the one side of the capacitance to a current charging source and switch control means response to a predetermined change in a signal at the input to enable charging of the capacitance to commence and responsive to a subsequent predetermined change at the output of the delay circuit at the end of said delay period to isolate the capacitance by rendering the switch non-conductive, thereby lifting the potential at the other side of the capacitance and allowing the potential at the gate of the first FET to be lifted above that of the supply rails and in so doing lifting the potential at the output.
The first circuit may further include a third field effect transistor having its gate connected to the input and its drain coupled to the input of the delay circuit.
The second circuit may include a further FET coupling the input to the gate of the second FET. The gate of the further FET is connected to the input and its drain is connected to the gate of the second transistor. Accordingly, when the signal at the input is low, the gate of the second transistor is high while that of the first transistor is low, and when the input is high, the reverse happens and accordingly both the first and second transistors are not conductive at the same time causing undesirable current drain.
Further, the switching means enables the gate of the first transistor to remain low until the bootstrapping operation is ready to occur via the delay circuit and thereafter the potential of the gate of the first transistor is lifted rapidly by the switching means being turned-off. As a result the buffer circuit is able to operate at high speed.
The switching means which may conveniently comprise a fourth field effect transistor having its source connected to the one side of the capacitance, may be controlled by logic means such as a NOR gate having one input connected to the drain of the third transistor and another input connected to the output of the delay circuit. By using directly connected components in this way the operating time of the drive circuit is kept to the minimum possible.
The capacitance may comprise the gate-channel of another field effect transistor. By using field effect transistors of depletion and enhancement types, as appropriate, the circuit may readily be constructed as an integrated circuit.
In order to overcome the possiblility of the potential at the output terminal dropping prematurely by the charge on the capacitance leaking away too quickly, means such as a depletion mode field effect transistor connected as a resistance, may be connected between the output terminal and the one supply rail to hold the output terminal at the rail voltage until the input goes low again.